View MT9M024_8585604.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MT9M024: 1/3-inch cmos digital image sensor features MT9M024_ds rev. g pub. 4/15 en 1 ?semiconductor components industries, llc,2015 1/3-inch cmos digital image sensor MT9M024 data sheet, rev. g for the latest data sheet, please visit www.onsemi.com features ? superior low-light performance ? hd video (720p60) ? linear or high dynamic range capture ? video/single frame modes ? on-chip ae and statistics engine ? parallel and serial output ? auto black level calibration ?context switching ?temperature sensor applications ? video surveillance ? 720p60 video applications ? high dynamic range imaging general description the on semiconductor MT9M024 is a 1/3-inch cmos digital image sensor with an active-pixel array of 1280h x 960v. it captures images in either linear or high dynamic range modes, with a rolling-shutter readout. it includes sophisticated camera functions such as auto exposure control, windowing, and both video and single frame modes. it is designed for both low light and high dynamic range scene performance. it is programmable through a simple two-wire serial interface. the MT9M024 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, includ- ing surveillance and hd video. *1.8v v dd _io is recommended due to better row noise per- formance table 1: key parameters parameter typical value optical format 1/3-inch (6 mm) active pixels 1280 x 960 = 1.2 mp pixel size 3.75 ? m color filter array rgb bayer or monochrome shutter type electronic rolling shutter input clock range 6 C 50 mhz output clock maximum 74.25 mhz output serial hispi 12-, 14-, or 20-bit parallel 12-bit frame rate full resolution 45 fps 720p 60 fps responsivity 5.48 v/lux-sec snr max 43.9 db maximum dynamic range >115 db supply voltage i/o 1.8 or 2.8v* digital 1.8 v analog hispi 2.8 v0.4 v or 1.8 v power consumption (typical) 270 mw (1280 x 720 60 fps parallel output linear mode) 460 mw (1280 x 720 60 fps parallel output hdr mode) operating temperature (ambient) -t a C30 c to + 70 c (surveillance) package options 9x9 mm ibga bare die
MT9M024_ds rev. g pub. 4/15 en 2 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description MT9M024ia3xtc-dpbr 1.2 mp 1/3" cis dry pack with protective film, double side bbar glass MT9M024ia3xtc-drbr 1.2 mp 1/3" cis dry pack with out protective film, do uble side bbar glass MT9M024ia3xtm-dpbr 1.2 mp 1/3" cis dry pack with protective film, double side bbar glass MT9M024ia3xtm-drbr 1.2 mp 1/3" cis dry pack with out protective film, do uble side bbar glass
MT9M024_ds rev. g pub. 4/15 en 3 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 high dynamic range mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 real-time context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 power-on reset and standby timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
MT9M024_ds rev. g pub. 4/15 en 4 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: typical configuration: serial fo ur-lane hispi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 3: typical configuration: parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 figure 4: 9 x 9 mm 63-ball ibga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 figure 5: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 6: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 7: imaging a scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 8: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 9: default pixel output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 10: lv format options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 11: hispi transmitter and receiver interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 12: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 13: block diagram of dll timing ad justment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 14: delaying the clock with respect to data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 15: delaying data with respect to the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 16: line timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 17: hdr data compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 18: pll-generated master clock pll setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 19: eight pixels in normal and co lumn mirror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: six rows in normal and row mi rror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 21: frame format with em bedded data lines enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 22: format of embedded data output within a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 23: format of embedded statistics ou tput within a frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 24: single read from random locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 25: single read fr om current location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 26: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 27: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 29: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 30: quantum efficiency ? color sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 31: estimated quantum efficiency ? monochrome sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 32: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 33: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 34: power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 35: differential output voltage for clock or data pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 36: eye diagram for clock and data signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 37: skew within the phy and output channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 38: power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 39: power down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 40: 63-ball ibga package outline dr awing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
MT9M024_ds rev. g pub. 4/15 en 5 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor list of tables list of tables table 1: key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 1: pin descriptions, 9 x 9 mm, 63-ball ibga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 2: digital gain control for odd and even x_addr_start (r0x3004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 3: frame time (example based on 1280 x 960, 45 frames per second) . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 4: frame time: long integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 5: knee points for compression to 14 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 6: knee points for compression to 12 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7: digital gain setting for each t1/t2 and t2/t3ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 8: real-time context-switch registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 9: test pattern modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 10: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 11: i/o timing characteristics (2.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 12: i/o timing characteristics (1.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 13: i/o rise slew rate (2.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 14: i/o fall slew rate (2.8v v dd _io) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 15: i/o rise slew rate (1.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 16: i/o fall slew rate (1.8v v dd _io) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 17: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 18: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 19: operating current consumption in pa rallel output and linear mode . . . . . . . . . . . . . . . . . . . . . . . .47 table 20: operating current consumption in pa rallel output and hdr mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 21: operating currents in hispi output and linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 22: operating current in hispi output and hdr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 23: standby current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 24: input voltage and current (hispi power supply 0.4 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 25: input voltage and current (hispi power supply 1.8 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 26: rise and fall times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 27: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 28: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
MT9M024_ds rev. g pub. 4/15 en 6 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor general description general description the on semiconductor MT9M024 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. the default mode output is a 960p- resolution image at 45 frames per second (fps). in linear mode, it outputs 12-bit raw data, using either the parallel or serial (hispi?) output ports. in high dynamic range mode, it outputs 12-bit compressed data usin g parallel output or 12-bit or 14-bit compressed or 20-bit linearized data using the hispi port. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. the MT9M024 includes additi onal features to allow ap plication-specific tuning: windowing and offset, ad justable auto-exposure control, auto black level correction, and on-board temperature sensor. optional regi ster information and histogram statistic information can be embedded in first and last 2 lines of the image frame. the sensor is designed to operate in a wide temperature range (?30c to +70c). functional overview the MT9M024 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 mhz the maximum output pixel rate is 74.25 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor. figure 1: block diagram user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.2 mp active- pi xel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and control registers active pixel sensor (aps) array pll memory otpm timing and control (sequencer) analog processing and a/d conversion auto exposure and stats engine pixel data path (signal processing) external clock parallel output two-wire serial interface trigger power
MT9M024_ds rev. g pub. 4/15 en 7 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor functional overview readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correc tion and gain), and then through an analog- to-digital converter (adc). th e output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and appl ies digital gain). the sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 20-bit per pixel value. a compressing mode is further offered to allow this 20-bit pixel valu e to be transmitted to the host system as a 12-bit value with close to zero loss in image quality. the pixel data are output at a rate of up to 74.25 mp/s, in parallel to frame and li ne synchronization signals. figure 2: typical configuration: serial four-lane hispi interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. the parallel interface output pads can be left un connected if the serial output interface is used. 5. on semiconductor recommends that 0.1f and 10f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. check the mt9m02 4 demo headboard schematics for circuit recom- mendations. 6. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 7. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. v dd _io v dd _slvs v dd _pll v dd v aa v dd v aa v aa _pix master clock (6C50 mhz) s data sclk reset_bar test extclk d gnd a gnd digital ground analog ground digital core power 1 hispi power 1 analog power 1 to controller from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k 2 1.5k 2, 3 analog power 1 vaa_pix slvsc_n slvsc_p slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p slvs3_n v dd _slvs trigger oe_bar standby s addr
MT9M024_ds rev. g pub. 4/15 en 8 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor functional overview figure 3: typical configuration: parallel pixel data interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. on semiconductor recommends that 0.1f and 10f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. check the demo headboard schematics for circuit recommenda- tions. 5. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. 7. the serial interface output pads and vddslvs can be left unconnected if the parallel output inter- face is used. v dd master clock (6C50 mhz) s data sclk test frame_valid d out [11:0] extclk d gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk reset_bar v dd _io digital i/o power 1 1.5k 2 1.5k 2, 3 v aa vaa_pix analog power 1 vdd_pll pll power 1 analog power 1 vaa_pix v dd _io v dd _pll v dd v aa trigger oe_bar standby a gnd s addr
MT9M024_ds rev. g pub. 4/15 en 9 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor functional overview figure 4: 9 x 9 mm 63-ball ibga package a b c d e f g h top view (ball down) slvs0n slvs0p slvs1n slvs1p v dd standby v dd _pll slvscn slvscp slvs2n slvs2p v dd v aa v aa extclk v dd _ slvs slvs3n slvs3p d gnd v dd a gnd s addr s clk s data d gnd d gnd v dd v aa _pix v aa _pix line_ valid frame_ valid pixclk flash d gnd v dd _io nc d out 8 d out 9d out 10 d out 11 d gnd v dd _io test d out 4d out 5d out 6d out 7d gnd v dd _io trigger oe_bar d out 0d out 1d out 2d out 3d gnd v dd _io v dd _io reset_ bar 12 3 567 8 4 v dd a gnd nc reserved
MT9M024_ds rev. g pub. 4/15 en 10 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor functional overview table 1: pin descriptions, 9 x 9 mm, 63-ball ibga name ibga pin type description slvs0n a2 output hispi serial data, lane 0, differential n. slvs0p a3 output hispi serial data, lane 0, differential p. slvs1n a4 output hispi serial data, lane 1, differential n. slvs1p a5 output hispi serial data, lane 1, differential p. standby a8 input standby-mode enable pin (active high). v dd _pll b1 power pll power. slvscn b2 output hispi serial ddr clock differential n. slvscp b3 output hispi serial ddr clock differential p. slvs2n b4 output hispi serial data, lane 2, differential n. slvs2p b5 output hispi serial data, lane 2, differential p. v aa b7, b8 power analog power. extclk c1 input external input clock. v dd _slvs c2 power hispi power. slvs3n c3 output hispi serial data, lane 3, differential n. slvs3p c4 output hispi serial data, lane 3, differential p. d gnd c5, d4, d5, e5, f5, g5, h5 power digital ground. v dd a6, a7, b6, c6, d6 power digital power. a gnd c7, c8 power analog ground. s addr d1 input two-wire serial address select. s clk d2 input two-wire serial clock input. s data d3 i/o two-wire serial data i/o. v aa _pix d7, d8 power pixel power. line_valid e1 output asserted when d out line data is valid. frame_valid e2 output asserted when d out frame data is valid. pixclk e3 output pixel clock out. d out is valid on rising edge of this clock. v dd _io e6, f6, g6, h6, h7 power i/o supply power. d out 8 f1 output parallel pixel data output. d out 9 f2 output parallel pixel data output. d out 10 f3 output parallel pixel data output. d out 11 f4 output parallel pixe l data output (msb) test f7 input. manufacturing test enable pin (connect to d gnd ). d out 4 g1 output parallel pixel data output. d out 5 g2 output parallel pixel data output. d out 6 g3 output parallel pixel data output. d out 7 g4 output parallel pixel data output. trigger g7 input exposure synchronization input. oe_bar g8 input output enable (active low). d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output. d out 2 h3 output parallel pixel data output. d out 3 h4 output parallel pixel data output.
MT9M024_ds rev. g pub. 4/15 en 11 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor functional overview reset_bar h8 input asynchronous reset (active low). all settings are restored to factory default. flash e4 output flash control output. nc e7, e8 no connection. reserved f8 no connection. table 1: pin descriptions, 9 x 9 mm, 63-ball ibga name ibga pin type description
MT9M024_ds rev. g pub. 4/15 en 12 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor pixel data format pixel data format pixel array structure the MT9M024 pixel array is configured as 1412 columns by 1028 rows, (see figure 5). the dark pixels are optically black and are used internally to monitor black level. of the right 100 columns, 64 are dark pixels used for row noise correction. of the top 24 rows of pixels, 12 of the dark rows are used for black level correction. there are 1296 columns by 976 rows of optically active pixels. while the sensor's format is 1280 x 960, the additional active columns and active rows are included fo r use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. the pixel adjustment is always performed for monochrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. not all dummy pixels or barrier pixels can be read out. figure 5: pixel array description 2 light dummy + 4 barrier + 24 dark + 4 barrier + 6 dark dummy dark pixel barrier pixel light dummy pixel active pixel 2 light dummy + 4 barrier + 6 dark dummy 1412 2 light dummy + 4 barrier 2 light dummy + 4 barrier + 100 dark + 4 barrier 1028 1296 x 976 (1288 x 968 active) 4.86 x 3.66 mm 2 (4.83 x 3.63 mm 2 )
MT9M024_ds rev. g pub. 4/15 en 13 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor pixel data format figure 6: pixel color pattern detail (top right corner) default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 6). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in defa ult condition is that of pixel (112, 44). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 7. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced as shown in figure 7 on page 8. figure 7: imaging a scene active pixel (0,0) physical pixel (112, 44) row reado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction lens pixel (0,0) row readout order column readout order scene sensor (rear view)
MT9M024_ds rev. g pub. 4/15 en 14 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor pixel data format digital gain control MT9M024 supports four digital gains for the color channels: red, green1 (green pixels on the red rows), green2 (green pixels on the blue rows), and blue. digital gain control of the MT9M024 is dependent on the configurat ion of the x_addr_start register. table 4 illustrates how the digital gains are applied when x_addr_start is even or odd number. table 2: digital gain control for odd and even x_addr_start (r0x3004) pixels x_addr_start gain register red even red_gain r0x305a odd green1_gain r0x3056 green1 (on red rows) even green1_gain r0x3056 odd red_gain r0x305a green2 (on blue rows) even green2_gain r0x305c odd blue_gain r0x3058 blue even blue_gain r0x3058 odd green2_gain r0x305c
MT9M024_ds rev. g pub. 4/15 en 15 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor output data format output data format the MT9M024 image data is read out in a progressive scan. valid image data is surrounded by horizontal and vertical blanki ng (see figure 8). the amount of horizontal row time (in clocks) is programmable throug h r0x300c. the amount of vertical frame time (in rows) is programmable through r0x 300a. line_valid (lv) is high during the shaded region of figure 8. optional embedded register setup information and histo- gram statistic information are available in first 2 and last row of image data. figure 8: spatial illustration of image readout readout sequence typically, the readout window is set to a region including only active pixels. the user has the option of reading out dark regions of the ar ray, but if this is done, consideration must be given to how the sensor reads the dark regions for its own purposes. p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
MT9M024_ds rev. g pub. 4/15 en 16 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor output data format parallel output data timing the output images are divided into frames, which are further divided into lines. by default, the sensor produces 968 rows of 1284 columns each. the fv and lv signals indi- cate the boundaries between frames and lines, respectively. pixclk can be used as a clock to latch the data. for each pixclk cycle, with respect to the falling edge, one 12-bit pixel datum outputs on the d out pins. when both fv and lv are asserted, the pixel is valid. pixclk cycles that occur when fv is de-asserted are called vertical blanking. pixclk cycles that occur when only lv is de-asserted are called horizontal blanking. figure 9: default pixel output timing lv and fv the timing of the fv and lv outputs is closely related to the row time and the frame time. fv will be asserted for an integral number of row times, which will normally be equal to the height of the output image. lv will be asserted during the valid pixels of each row. the leading edge of lv will be offset from the leading edge of fv by 6 pixclk s. normally, lv will only be asserted if fv is asserted; this is configurable as described below. lv format options the default situation is for lv to be de-asser ted when fv is de-asserted. by configuring r0x306e[1:0], the lv signal can take two different output formats. the formats for reading out four lines and two vertical blanking lines are shown in figure 10. pixclk fv lv d out [11:0] p0 p1 p2 p3 p4 pn vertical blanking horiz blanking valid image data horiz blanking vertical blanking
MT9M024_ds rev. g pub. 4/15 en 17 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor output data format figure 10: lv format options the timing of an entire frame is shown in figure 16: ?line timing and frame_valid/ line_valid signals,? on page 15. serial output data timing the MT9M024 also uses on semiconductor' s high-speed serial pixel interface (?hispi?). the physical interface comprises di fferential serial data lines and a differential clock line. the protocol layer formats the da ta and synchronization signals separately, with sync codes defined for active image boundaries. figure 11 shows the configuration between the hispi transmitter and the receiver. there are two options for hispi output slvs or hivcm mode selectable through regist er 0x306e bit 9. setting this bit to 0 selects slvs ; setting the bit to 1 selects hivcm. figure 11: hispi transmitter and receiver interface block diagram hispi physical layer the hispi physical layer has four data lanes and an associated clock lane. depending on the sensor operating mode and da ta rate, it can be configured t o use either 2, 3, or 4 lanes. the phy will serialize a 12- to 20-bit data word and transmit each bit of data default continuous lv fv lv fv lv a camera containing the hispi transmitter a host (dsp) containing the hispi receiver dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0 tx phy0 rx phy0 dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0
MT9M024_ds rev. g pub. 4/15 en 18 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor output data format centered on a rising edge of the clock, the second on the following falling edge of clock. figure 12 shows bit transmission. in this example, the word is transmitted in order of msb to lsb. the receiver latches data at the rising and falling edge of the clock. figure 12: timing diagram dll timing adjustment the MT9M024 includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the rece iver circuits and can be used to compensate for skew introduced in pcb design. delay compensation may be set for clock and/or data lines in the hispi_timing register r0x31c0. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa- tion. figure 13: block diagram of dll timing adjustment c p dn . . msb lsb txpost dp cn 1 ui txpre delay delay delay delay delay data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane 3 clock_del[2:0] data0_del[2:0] data1_del[2:0] data2_del[2:0] data3_del[2:0]
MT9M024_ds rev. g pub. 4/15 en 19 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor output data format figure 14: delaying the clock with respect to data figure 15: delaying data with respect to the clock datan (datan_del = 000) cp (clock_del = 000) cp (clock_del = 001) cp (clock_del = 010) cp (clock_del = 011) cp (clock_del = 100) cp (clock_del = 101) c p (clock_del = 110) cp (clock_del =111) increasing clock_del [2:0] increases clock delay 1 ui 1 ui t dllstep cp ( clock_del = 000) datan (datan_del = 000) datan(datan_del = 001) datan(datan_del = 010) datan(datan_del = 011) datan(datan_del = 100) datan(datan_del = 101) datan(datan_del = 110) datan(datan_del = 111) increasing datan_del [2:0] increases data delay
MT9M024_ds rev. g pub. 4/15 en 20 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor output data format frame time the pixel clock (pixclk) represents the time needed to sample 1 pixel from the array. the sensor outputs data at the maximum rate of 1 pixel per pixclk. one row time ( t row) is the period from the first pixel output in a row to the first pixel output in the next row. the row time and frame time are defined by equations in table 3. figure 16: line timing and frame_valid/line_valid signals sensor timing is shown in terms of pixel clock cycles (see figure 8 on page 10). the recommended pixel clock frequency is 74.25 mh z. the vertical blanking and the total frame time equations assume that the integrat ion time (coarse integration time plus fine integration time) is less than the number of active lines plus the blanking lines: window height + vertical blanking (eq 1) if this is not the case, the number of integr ation lines must be used instead to determine the frame time, (see table 4). in this example, it is assumed that the coarse integration time control is programmed with 2000 rows and the fine shutter width total is zero. for master mode, if the integration time regi sters exceed the total readout time, then the vertical blanking time is inte rnally extended automatically to adjust for the additional integration time required. this extended value is not written back to the frame_length_lines register. the frame_length_lines register can be used to adjust frame-to-frame readout time. this register do es not affect the exposure time but it may extend the readout time. table 3: frame time (example based on 1280 x 960, 45 frames per second) parameter name equation default timing at 74.25 mhz aactive data time context a: r0x3008 - r0x3004 + 1 context b: r0x308e - r0x308a + 1 1280 pixel clocks = 17.23 ? s p1 frame start blanking 6 (fixed) 6 pixel clocks = 0.08 ? s p2 frame end blanking 6 (fixed) 6 pixel clocks = 0.08 ? s q horizontal blanking r0x300c - a 370 pixel clocks = 4.98 ? s a+q (trow) line (row) time r0x300c 1650 pixel clocks = 22.22 ? s v vertical blanking context a: (r0x300a-(r0x3006-r0x3002+1)) x (a + q) context b: ((r0x30aa-(r0x3090-r0x308c+1)) x (a + q) 49,500 pixel clocks = 666.66 ? s nrows x (a + q) frame valid time context a: ((r0x3006-r0x3002+1)*(a+q))-q+p1+p2 context b: ((r0x3090-r0x308c+1)*(a+q))-q+p1+p2 1,584,000 pixel clocks = 21.33ms f total frame time v + (nrows x (a + q)) 1,633,500 pixel clocks = 22.22ms p1 a q a q a p2 number of master clocks frame_valid line_valid ... ... ...
MT9M024_ds rev. g pub. 4/15 en 21 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor output data format note: the MT9M024 uses column parallel analog-digital converters; thus short line timing is not possi- ble. the minimum total line time is 1650 column s (horizontal width + horizontal blanking) for hdr mode and 1400 for linear mode. th e minimum horizontal blanking is 370. exposure total integration time is the result of co arse_integration_time and fine_integration_- time registers, and depends also on whether manual or automatic exposure is selected. the actual total integration time, t int is defined as: t int = t intcoarse - 410 - t intfine (eq 2) = (number of lines of integration x line time) - (410 pixel clocks of conversion time over- head) - (number of pixels of integration x pixel time) where: ? number of lines of integration (auto exposure control: enabled) when automatic exposure control (aec) is enabled, the number of lines of integra- tion may vary from frame to frame, with the limits controlled by r0x311e (mini- mum auto exposure time) and r0x311c (maximum auto exposure time). ? number of lines of integration (a uto exposure control: disabled) if aec is disabled, the number of lines of integration equals the value in r0x3012 (context a) or r0x3016 (context b). ? number of pixels of integration the number of fine shutter width pixels is independent of aec mode (enabled or disabled): ? context a: the number of pixels of integration equals the value in r0x3014. ? context b: the number of pixels of in tegration equals the value in r0x3018. max- imum value for t intfine is line length pixel clocks - 611 . typically, the value of the coarse_integration_ time register is limited to the number of lines per frame (which includes vertical blanki ng lines), such that the frame rate is not affected by the integration time. for more information on coarse and fine integration time settings li mits, please refer to the register reference document. note: in hdr mode, there are specific limitations on coarse_integration_time due to the number of line buffers available. please refer to the section called ?hdr specific exposure settings? on page 19. for best image quality, it is recommended that the integration time be set to two rows or greater for the shortest exposure, particularly for monochrome sensors. for linear mode, this would be the coarse integration time (r0x3012). for hdr mode, the integration time should be set such that the t3 exposure is 2 rows or greater. setting the exposure time to 1 row may result in non-uniformity between rows. table 4: frame time: long integration time parameter name equation (number of pixel clock cycles) default timing at 74.25 mhz f total frame time (long integration time) context a: (r0x3012 x (a + q)) + r0x3014 + p1 + p2 context b: (r0x3016 x (a + q)) + v r0x3018 + p1 + p2 3,300,012 pixel clocks = 44.44ms
MT9M024_ds rev. g pub. 4/15 en 22 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor high dynamic range mode high dynamic range mode by default, the sensor powers up in linear mode, however, the MT9M024 can be config- ured to run in hdr mode. the hdr scheme used is multi-exposure hdr. this allows the sensor to handle 120db of dynamic range. the sensor also features a linear mode. in hdr mode, the sensor sequentially captures three exposures by maintaining 3 separate read and reset pointers that are interleaved within the rolling shutter readout. the inter- mediate pixel values are stored in line buffers while waiting for the 3 exposures values to be present. as soon as a pixel's 3 exposure values are available, they are combined to create a linearized 20-bit value for each pixel?s response. this 20-bit value is then option- ally compressed back to a 12- or 14-bit value for output. for 14-bit mode, the compressing is lossless. in 12-bit mode, there is minimal data loss. figure 17 shows the hdr data compression: figure 17: hdr data compression signal response to light intensity digital output code k1 = knee point 1 k2 = knee point 2 pout = p decompressed linear output adc max code piece-wise compressed signal output from sensor
MT9M024_ds rev. g pub. 4/15 en 23 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor high dynamic range mode the hdr mode is selected when operation_mode_ctrl, r0x3082[1:0] = 0. further controls on exposure time limits and compressing are controlled by r0x3082[5:2], and r0x31d0. more details can be found in the MT9M024 register reference. in hdr mode, when compression is used, ther e are two types of knee-points: (i) t1/t2 and t2/t3 capture knee-points and (ii) p out and p out 2 compression knee-points (figure 17). aligning the capture knee-point s on top of the compression knee-points, can avoid code losses (snr loss) in the compression. table 5 and table 6 below show the knee points for the different modes. alternat ively, the sensor automatically reports the knee points and can be read directly from registers r0 x319a and r0x319c. table 5: knee points for compression to 14 bits t1/t2 exposure ratio (r1) r0x3082[3:2] p1 p out 1 = p1 p2 p out 2 = (p2 - p1)/ r1 + p out 1 t2/t3 exposure ratio (r2) r0x3082[5:4] p max p out max = (p max - p2)/ (r1*r2) + p out 2 4x 2 12 4096 2 14 7168 4x 2 16 10240 8x 2 17 10752 16x 2 18 11008 8x 2 12 4096 2 15 7680 4x 2 17 10752 8x 2 18 11264 16x 2 19 11520 16x 2 12 4096 2 16 7936 4x 2 18 11008 8x 2 19 11520 16x 2 20 11776 table 6: knee points for compression to 12 bits t1/t2 exposure ratio (r1) r0x3082[3:2] p1 p out 1 = p1 p2 p out 2 = (p2 - p1)/ (r1* 4)+ p out 1 t2/t3 exposure ratio (r2) r0x3082[5:4] p max p out max = (p max - p2)/ (r1*r2*4) + p out 2 4x 2 11 2048 2 14 2944 4x 2 16 3712 8x 2 17 3840 16x 2 18 3904 8x 2 11 2048 2 15 3008 4x 2 17 3776 8x 2 18 3904 16x 2 19 3968 16x 2 11 2048 2 16 3040 4x 2 18 3808 8x 2 19 3936 16x 2 20 4000
MT9M024_ds rev. g pub. 4/15 en 24 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor high dynamic range mode hdr specific exposure settings in hdr mode, pixel values are stored in line buffers while waiting for all 3 exposures to be available for final pixel data combination. there are 42 line buffers used to store inter- mediate t1 data. due to this limitation, the maximum coarse integration time possible is equal to 42*t1/t2 lines. for example, if r0x3082[3:2] = 2, the sensor is set to have t1/t2 ratio = 16x. therefore the maximum number of integration lines is 42*16 = 672 lines. if coarse integration time is greater than this, the t2 integration time will stay at 42. the sensor will calculate the ratio internally,enabling the linearization to be performed. if companding is being than relinearization would still follow the programmed ratio. for example if the t1/t2 ratio was programmed to 16x but coarse integration was increased beyond 672 than one would still use the 16x relinearization formulas. an additional limitation is the maximum numb er of exposure lines in relation to the frame_length_lines register. in linear mode, as described on page 20, maximum coarse_integration_time = frame_length_lines - 1. however in hdr mode, since the coarse integration time register controls t1, the max coarse_integration time is frame_length_lines - 45. putting the two criteria listed above toge ther, it can be summarized as follows: (eq 3) in hdr mode, subline integration is not utilized. as such, fine integration time register changes will have no effect on the image. there is also a limitation of the minimum nu mber of exposure lines that can be used. this is summarized in the following formula: (eq 4) due to limitation on the internal floating po int calculation, the exact ratio specified by the ratio_t2_t3 (r0x3082[5:4]) may not be achievable. when using companded output in combination with certain exposure ratios (other than t1/t2 = 16x and t2/t3 = 16x), digital gain need s to be set to a fixed value. table below provides the proper digital gain settings for each t1/t2 and t2/t3 ratio. table 7: digital gain setting for each t1/t2 and t2/t3ratio t1/t2 ratio t2/t3 ratio setting for digital gain register (0x305e context a or 0x30c4 context b) 4 4 0x02h 4 8 0x04h 416 0x08h 8 4 0x04h 8 8 0x08h 816 0x10h 16 4 0x08h 16 8 0x10h 16 16 any legal value maximum coarse_integration_time min imum 42 t1 t2, frame_length_lines 45 ? ? ? ?? = minimum coarse_integration_time 0.5 ?? *t1 t2 ? ?? ? t2 t3 ? ?? =
MT9M024_ds rev. g pub. 4/15 en 25 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor high dynamic range mode motion compensation in typical multi-exposure hdr systems, moti on artifacts can be created when objects move during the t1, t2 or t3 integration time. when this happens , edge artifacts can potentially be visible and might look like a ghosting effect. to correct this feature, the MT9M024 has special 2d motion compensation circuitry that detects motion artifacts and corrects the image accordingly. there are two motion compensation options available. one using the default hdr motion compensation by setting r0x318c[14] = 1. additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application. these can be set in r0x318c?r0x3190. the other is using the dlo method of hdr combin ation. when using dlo, r0x318c[14] is ignored. dlo is enabled by setting r0x3190[13] = 1. noise filt ering is enabled by setting r0x3190[14] = 1. for more information, please refer to the MT9M024 register reference document.
MT9M024_ds rev. g pub. 4/15 en 26 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor real-time context switching real-time context switching in the MT9M024, the user may switch between two full register sets (listed in table 8) by writing to a context switch change bit in r0x30b0[13]. this context switch will change all registers (no shadowing) at the frame start time and have the new values apply to the immediate next exposure and readout time. features see the MT9M024 register reference for additional details. reset the MT9M024 may be reset by using reset_bar (active low) or the reset register. hard reset of logic the reset_bar pin can be connected to an external rc circuit for simplicity. the recommended rc circuit uses a 10k ? resistor and a 0.1 ? f capacitor. the rise time for the rc circuit is 1 ? s maximum. soft reset of logic soft reset of logic is controlled by the r0x301a reset register. bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configu- ration. furthermore, by asserting the soft rese t, the sensor aborts the current frame it is processing and starts a new fram e. this bit is a self-resetting bit and also returns to ?0? during two-wire seri al interface reads. table 8: real-time context-switch registers register description register number context a context b y_addr_start r0x3002 r0x308c x_addr_start r0x3004 r0x308a y_addr_end r0x3006 r0x3090 x_addr_end r0x3008 r0x308e coarse_integration_time r0x3012 r0x3016 fine_integration_time r0x3014 r0x3018 y_odd_inc r0x30a6 r0x30a8 column gain r0x30b0[5:4] r0x30b0[9:8] green1_gain (greenr) r0x3056 r0x30bc blue_gain r0x3058 r0x30be red_gain r0x305a r0x30c0 green2_gain (greenb) r0x305c r0x30c2 global_gain r0x305e r0x30c4 frame_length_lines r0x300a r0x30aa digital_binning r0x3032[1:0] r0x3032[5:4] operation_mode_ctrl 0x3082 0x3084
MT9M024_ds rev. g pub. 4/15 en 27 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features clocks the MT9M024 requires one clock input (extclk). pll-generated master clock the pll contains a prescaler to divide th e input clock applied on extclk, a vco to multiply the prescaler output, and two divider stages to generate the output clock. the clocking structure is shown in figure 18. pl l control registers can be programmed to generate desired master clock frequency. note: the pll control registers must be programm ed while the sensor is in the software standby state. the effect of programming the pll divisors while the sensor is in the streaming state is undefined. figure 18: pll-generated master clock pll setup the pll is enabled by default on the MT9M024. to configure and use the pll: 1. bring the MT9M024 up as normal; make sure that f extclk is between 6 and 50mhz and ensure the sensor is in software standb y (r0x301a-b[2]= 0). pll control registers must be set in software standby. 2. set pll_multiplier, pre_pll_clk_div, vt_sys _clk_siv, and vt_pix_clk_div based on the desired input (f extclk ) and output ( f pixclk ) frequencies. determine the m, n, p1, and p2 values to achieve the desired f pixclk using this formula: f pixclk = ( f extclk m) / (n p1 x p2) where m = pll_multiplier n = pre_pll_clk_div p1 = vt_sys_clk_div p2 = vt_pix_clk_div 3. wait 1ms to ensure that the vco has locked. 4. set r0x301a[2]=1 to enable streaming and to switch from extclk to the pll-gener- ated clock. notes: 1. the pll can be bypassed at any time (sensor will run directly off extclk) by setting r0x30b0[14]=1. the pll is always bypassed in software standby mode. to disable the pll, the sensor must be in standby mode (r0x301a[2] = 0) 2. the following restrictions apply to the pll tuning parameters: pre pll div (pfd) pre _p ll _ clk _ div extclk pll multiplier (vco) pll output div 1 sysclk pixclk vt _p ix _ clk _ div vt _ s y s _ clk _ div pll input clock pll output clock pll output div 2 pll_multiplier 32 m 255 ?? 1n 63 ??
MT9M024_ds rev. g pub. 4/15 en 28 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features 3. the vco frequency, defined as must be within 384-768 mhz. 4. when pll_multiplier is odd, 2 mhz <= fextclk / n <= 24 mhz 5. if using hispi output mode, use the fo llowing settings for p2 (vt_pix_clk_div). 5a. if 20-bit mode (4 lanes): set p2 (r0x302a) = 5 5b. if 12-/14-bit mode (3 lanes): set p2 (r0x302a) = 5 5c. if 12-bit mode (2 lanes): set p2 (r0x302a) = 6 5d. if 14-bit mode (2 lanes): set p2 (r0x302a) = 7 the user can utilize the register wizard tool accompanying devware to generate pll settings given a supplied input clock and desired output frequency. spread-spectrum clocking to facilitate improved emi performance, the external clock input allows for spread spec- trum sources, with no impact on image quality. limits of the spread spectrum input clock are: ? 5% maximum clock modulation ? 35 khz maximum modulation frequency ? accepts triangle wave modulation, as well as sine or modified triangle modulations. stream/standby control the sensor supports two standby modes: hard standby and soft standby. in both modes, external clock can be optionally di sabled to further minimize power consump- tion. if this is done, then the ?power-up sequence? on page 54 must be followed. soft standby soft standby is a low power state that is controlled through register r0x301a[2]. depending on the value of r0x301a[4], the sens or will go to standby after completion of the current frame readout (default behavior) or after the completion of the current row readout. when the sensor comes back from soft standby, previously written register settings are still maintained. soft standby wi ll not occur if the trigger pin is held high. a specific sequence needs to be followed to enter and exit from soft standby. entering soft standby: 1. set r0x301a[2] = 0 and drive the trigger pin low. 2. external clock can be turned off to fu rther minimize power consumption (optional) exiting soft standby: 1. enable external clock if it was turned off 2. r0x301a[2] = 1 or drive the trigger pin high. 1p116 (p1 = 1, 2, 4, 6,8, 10, 12, 14, 16) ?? 4p216 ?? f vco f extclk m ? n ? =
MT9M024_ds rev. g pub. 4/15 en 29 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features hard standby hard standby puts the sensor in lower power state; previously written register settings are still maintained. a specific sequence needs to be followed to enter and exit from hard standby. entering hard standby: 1. r0x301a[8] = 1 2. assert standby pin 3. external clock can be turned off to fu rther minimize power consumption (optional) exiting hard standby: 1. enable external clock if it was turned off 2. de-assert standby pin 3. set r0x301a[8] = 0 window control registers x_addr_start, x_addr_end, y_addr_s tart, and y_addr_end control the size and starting coordinates of the image window. the exact window height and width out of the sensor is determined by the difference between the y address start and end registers or the x address start and end registers, respectively. the MT9M024 allows different window sizes for context a and context b. blanking control horizontal blank and vertical blank times are controlled by the line_length_pck and frame_length_lines registers, respectively. ? horizontal blanking is specified in terms of pixel clocks. it is calculated by subtracting the x window size from the line_length_pck register. the minimum horizontal blanking is 370 pixel clocks. ? vertical blanking is specified in terms of numbers of lines. it is calculated by subtracting the y window size from the frame_length_lines register. the minimum vertical blanking is 26 lines. the actual imager timing can be calculat ed using table 3 on page 15 and table 4 on page 16, which describe the line timing and fv/lv signals. when in hdr mode, the maximum size is 1280 x 960.
MT9M024_ds rev. g pub. 4/15 en 30 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features readout modes digital binning by default, the resolution of the output ima ge is the full width and height of the fov as defined above. the output resolution can be reduced by digital binning. for rgb and monochrome mode, this is set by the register r0x3032. for context a, use bits [1:0], for context b, use bits [5:4]. available settings are: 00 = no binning 01 = horizontal binning 10 = horizontal and vertical binning binning gives the advantage of reducing nois e at the cost of reduced resolution. when both horizontal and vertical binning are us ed, a 2x improvement in snr is achieved, therefore improving low light performance. binning results in a smaller resolution image, but the fovs between the binned and unbinned images are the same. bayer space resampling all of the pixels in the fov contribute to th e output image in digital binning mode. this can result in a more pleasing output image with reduced subsampling artifacts. it also improves low-light performance. for rgb mode, resampling can be enabled by setting of register 0x306e[4] = 1. mirror column mirror image by setting r0x3040[14] = 1, the readout order of the columns is reversed, as shown in figure 19. the starting bayer color pixel is main tained in this mode by a 1-pixel shift in the imaging array. when using horizontal mirror mode, the user must retrigger column correction. please refer to the column correction section to see the procedure for column correction retrig- gering. bayer resampling must be enabled, by setting bit 4 of register 0x306e[4] = 1. figure 19: eight pixels in normal and column mirror readout modes row mirror image by setting r0x3040[15] = 1, the readout order of the rows is reversed as shown in figure 20. the starting bayer color pixel is main tained in this mode by a 1-pixel shift in the imaging array. when using horizontal mi rror mode, the user must retrigger column correction. please refer to the column co rrection section to see the procedure for column correction retriggering. g0[1 1:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] g3[11:0] r3[11:0] g2[11:0] r2[11:0] g1[11:0] r1[11:0] d out [11:0] lv normal readout d out [11:0] reverse readout g3[11:0] r3[11:0] g0[11:0] r0[11:0]
MT9M024_ds rev. g pub. 4/15 en 31 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features figure 20: six rows in normal and row mirror readout modes maintaining a constant frame rate maintaining a constant frame rate while contin uing to have the ability to adjust certain parameters is the desired scenario. this is not always possible, however, because register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the prev ious frame. therefore, any register changes that could affect the row time or the set of rows sampled causes the shutter pointer to start over at the beginning of the next frame. by default, the following register fields caus e a ?bubble? in the output rate (that is, the vertical blank increases for one frame) if they are written in video mode, even if the new value would not change the resulting frame rate. the following list shows only a few examples of such registers; a full listing ca n be seen in the MT9M024 register reference. ?x_addr_start ? x_addr_end ? y_addr_start ? y_addr_end ? frame_length_lines ? line_length_pclk ? coarse_integration_time ? fine_integration_time ?read_mode the size of this bubble is (integration_time t row ), calculating the row time according to the new settings. the coarse_integration_time and fine_integration_time fields may be written to without causing a bubble in the output rate under certain circumstances. because the shutter sequence for the next frame often is active during the output of the current frame, this would not be possible without special provisions in the hardware. writes to these registers take effect two frames after the frame they are written, which allows the integration time to increase without interr upting the output or producing a corrupt frame (as long as the change in integration time does not affect the frame time). synchronizing register writes to frame boundaries changes to most register fields that affect th e size or brightness of an image take effect on two frames after the one during which th ey are written. these fields are noted as ?synchronized to frame boundaries? in the MT9M024 register reference. to ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of fv and before the trailing edge of fv. row0 [11:0] row1 [11:0] row2 [11:0] row3 [11:0] row4 [11:0] row5 [11:0] row5 [11:0] row4[11:0] row3 [11:0] row2[11:0] row1 [11:0] row0[11:0] d out [11:0] fv normal readout d out [11:0] reverse readout
MT9M024_ds rev. g pub. 4/15 en 32 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features as a special case, in single frame mode, register writes that occur after fv but before the next trigger will take effect immediately on the next frame, as if there had been a restart. however, if the trigger for the next frame occurs during fv, register writes take effect as with video mode. fields not identified as being frame-synchronized are updated immediately after the register write is completed. the effect of thes e registers on the next frame can be difficult to predict if they affect the shutter pointer. restart to restart the MT9M024 at any time during the operation of the sensor, write a ?1? to the restart register (r0x301a[1] = 1). this has tw o effects: first, the current frame is inter- rupted immediately. second, any writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in video mode). the current row completes before the new frame is started, so the time between issuing the restart and the beginning of the next frame can vary by about t row . image acquisition modes the MT9M024 supports two image acquisition modes: video(master) and single frame. video the video mode takes pictures by scanning the rows of the sensor twice. on the first scan, each row is released from reset, starting the exposure. on the second scan, the row is sampled, processed, and returned to the reset state. the exposure for any row is there- fore the time between the first and second sc ans. each row is exposed for the same dura- tion, but at slightly different point in time, which can cause a shear in moving subjects as is typical with electronic rolling shutter sensors. single frame the single-frame mode operates similar to th e video mode. it also scans the rows of the sensor twice, first to reset the rows and second to read the rows. unlike video mode where a continuous stream of images are output from the image sensor, the single-frame mode outputs a single frame in response to a high state placed on the trigger input pin. as long as the trigger pin is held in a high state, new images will be read out. after the trigger pin is returned to a low state, the image sensor will not output any new images and will wait for the next high state on the trigger pin. the trigger pin state is detected during the ve rtical blanking period (i.e. the fv signal is low). the pin is level sensitive rather than edge sensitive. as such, image integration will only begin when the sensor detects that the trigger pin has been held high for 3 consecutive clock cycles. if the trigger signal is applied to multiple sensors at the same time, the single frame output of the sensors will be synchronized to within 1 pixclk if is pll disabled or 2 pixclks if pll is enabled. during integration time of single-frame mode and video mode, the flash output pin is at high. continuous trigger in certain applications, multiple sensors need to have their video streams synchronized (e.g. surround view or panorama view applications). the trigger pin can also be used to synchronize output of multiple image sens ors together and still get a video stream. this is called continuous trigger mode. co ntinuous trigger is enabled by holding the
MT9M024_ds rev. g pub. 4/15 en 33 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features trigger pin high. alternatively, the trigger pin can be held high until the stream bit is enabled (r0x301a[2]=1) then can be re leased for continuous synchronized video streaming. if the trigger pins for all connected mt 9m024 sensors are connected to the same control signal, all sensors will receive the trigger pulse at the same time. if they are configured to have the same frame timing, then the usage of the trigger pin guaran- tees that all sensors will be synchronized within 1 pixclk cycle if pll is disabled, or 2 pixclk cycles if pll is enabled. with continuous trigger mode, the applicatio n can now make use of the video streaming mode while guaranteeing that all sensor outputs are synchron ized. as long as the initial trigger for the sensors takes place at the same time, all subsequent video streams will be synchronous. temperature sensor the MT9M024 sensor has a built-in ptat-bas ed temperature sensor, accessible through registers, that is capable of me asuring die junction temperature. the temperature sensor can be enabled by writing r0x30b4[0]=1 and r0x30b4[4]=1. after this, the temperature sensor output value can be read from r0x30b2[10:0]. the value read out from the temperature sens or register is an adc output value that needs to be converted downstream to a final temperature value in degrees celsius. since the ptat device characteristic response is qu ite linear in the temperature range of oper- ation required, a simple linear function in th e format of listed in the equation below can be used to convert the adc output value to the final temperature in degrees celsius. (eq 5) for this conversion, a minimum of 2 known points are needed to construct the line formula by identifying the slope and y-intercept "t 0 ". these calibration values can be read from registers r0x30c6 and r0x30c8 which correspond to value read at 70 c and 55 c respectively. once read, the slope and y- intercept values can be calculated and used in the above equation. for more information on the temperature sensor registers, refer to the MT9M024 register reference. temperature slope r0x30b2 10:0 ?? t + ? 0 =
MT9M024_ds rev. g pub. 4/15 en 34 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features automatic exposure control the integrated automatic exposure control (aec) is responsible for ensuring that optimal settings of exposure and gain are computed and updated every other frame. aec can be enabled or disabled by r0x3100[0]. when aec is disabled (r0x3100[0] = 0), the sensor uses the manual exposure value in coarse and fine shutter width registers and th e manual gain value in the gain registers. when aec is enabled (r0x3100[0]=1), the tar get luma value in linear mode is set by r0x3102. for the MT9M024 this target luma has a default value of 0x0800 or about half scale. for hdr mode, the luma target maximum auto exposure value is limited by r0x311c; the minimum auto exposure is limited by r0x311e. these values are in units of line-times. the exposure control measures current scene luminosity by accumulating a histogram of pixel values while reading out a frame. it then compares the current luminosity to the desired output luminosity. finally, the appropriate adjustments are made to the expo- sure time and gain. all pixels are used, regardless of color or mono mode. in hdr mode, the coarse and fine integration time is the longest integration time of the three integra- tion, the other two shorter integration are generated automatically base on the pre- defined exposure ratios. when using non- default hdr exposure ratios, auto_dg_en should not be enabled (r0x3100[4] = 0) due to required digital gains as documented in table 7, ?digital gain setting for each t1/t2 and t2/t3ratio,? on page 19. embedded data and statistics the MT9M024 has the capability to output image data and statistics embedded within the frame timing. there are 2 types of information embedded within the frame readout: 1. embedded data: if enabled, these are displayed on the 2 rows immediately before the first active pixel row is displayed. 2. embedded statistics: if enabled, these ar e displayed on the 2 rows immediately after the last active pixel row is displayed. note: embedded data and embedded statistics must be enabled or disabled together. figure 21: frame format with embedded data lines enabled image register data status & statistics data hblank vblank
MT9M024_ds rev. g pub. 4/15 en 35 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features embedded data the embedded data contains the configurat ion of the image being displayed. this includes all register settings used to capture the current frame. the registers embedded in these rows are as follows: line 1: registers r0x3000 to r0x312f line 2: registers r0x3136 to r0x31bf, r0x31d0 to r0x31ff note: all non-defined registers will have a value of 0. in parallel mode, since the pixel word depth is 12-bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where the register data will be broken up into 8msb and 8lsb. the alignment of the 8bit data will be on the 8msb bits of the 12-bit pixel word. for example, if a register value of 0x1234 is to be transmitted, it wi ll be transmitted over 2, 12-bit pixels as follows: 0x120, 0x340. the first pixel of each line in the embedded data is a tag value of 0x0a0. this signifies that all subsequent data is 8 bit data aligned to the msb of the 12-bit pixel. the figure below summarizes how the embedded data transmission looks like. it should be noted that data, as shown in figure 2 2, is aligned to the msb of each word: figure 22: format of embedde d data output within a frame the data embedded in these rows are as follows: ?0x0a0 - identifier ? 0xaa0 ? register address msb of the first register ?0xa50 ? register address lsb of the first register ?0x5a0 ? register value msb of the first register addressed ?0x5a0 ? register value lsb of the first register addressed ?0x5a0 ? register value msb of the register at first address + 2 ?0x5a0 ? register value lsb of the register at first address + 2 ?0x5a0 ?etc. {register_ value_lsb} 8'h5a data line 1 data line 2 8'h5a 8'haa {register_ address_msb} 8'ha5 {register_ address_lsb} 8'h5a {register_ value_msb} 8'h5a {register_ value_lsb} data_format_ code =8'h0a 8'haa {register_ address_msb} 8'ha5 {register_ address_lsb} 8'h5a {register_ value_msb} 8'h5a data_format_ code =8'h0a
MT9M024_ds rev. g pub. 4/15 en 36 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features embedded statistics the embedded statistics cont ain frame identifiers and hi stogram information of the image in the frame. this can be used by do wnstream auto-exposure algorithm blocks to make decisions about exposure adjustment. this histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 2 12 , 120 evenly spaced bins for values 2 12 to 2 16 , 60 evenly spaced bins for values 2 16 to 2 20 . in hdr with a 16x exposure ratio, this approximately corre- sponds to the t1, t2, t3 exposures respectively. the first pixel of each line in the embedded statistics is a tag value of 0x0b0. this signi- fies that all subsequent statistics data is 10 bit data aligned to the msb of the 12-bit pixel. the figure below summarizes how the embedded statistics transmission looks like. it should be noted that data, as shown in fi gure 23, is aligned to the msb of each word: figure 23: format of embedded st atistics output within a frame the statistics embedded in these rows are as follows: line 1: ? 0x0b0 - (identifier) ? register 0x303a - frame_count ? register 0x31d2 - frame id ? histogram data - histogram bins 0-243 line 2: ?0x0b0 (identifier) ?mean ?histogram begin ?histogram end ?low end histogram mean ? percentage of pixels below low end mean ? normal absolute deviation gain digital gain digital gain can be controlled globally by r0x305e (context a) or r0x30c4 (context b). there are also registers that allow individual control over each bayer color (greenr, greenb, red, blue). {2'b00,frame _count msb} {2'b00,frame _count lsb} {2'b00,frame _id msb} {2'b00,frame _id lsb} histogram bin0 [19:10] histogram bin0 [9:0] histogram bin1 [19:10] histogram bin1 [9:0] # words = 10'h1ec data_format_ code = 8'h0b histogram bin243 [19:10] histogram bin243 [9:0] # words = 10'h00c data_format_ code = 8'h0b mean [19:10] mean [9:0] histbegin [19:10] histbegin [9:0] histend [19:10] histend [9:0] lowendmean [19:10] lowendmean [9:0] perc_lowend [19:10] perc_lowend [9:0] norm_abs_ dev [19:10] norm_abs_ dev [9:0] 8'h07 8'h07 8'h07 stats line 1 stats line 2
MT9M024_ds rev. g pub. 4/15 en 37 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features the format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain setting and 0b00110000 represents a 1.5x gain setting. the step size for yyyyy is 0.03125 while the step size for xxx is 1. therefore to set a gain of 2.09375 one would set digital gain to 01000011. analog gain the MT9M024 has a column parallel architectu re and therefore has an analog gain stage per column. there are 2 stages of analog gain, the first stag e can be set to 1x, 2x, 4x or 8x. this can be set in r0x30b0[5:4](context a) or r0x30b0[9:8] (context b). the second stage is capable of setting an additional 1x or 1.25x gain which can be set in r0x3ee4[9:8]. this allows the maximum possible analog gain to be set to 10x. black level correction black level correction is handled automatica lly by the image sensor . no adjustments are provided except to enable or disable this fe ature. setting r0x30ea[15] disables the auto- matic black level correction. de fault setting is for automatic black level calibration to be enabled. the automatic black level correction measures the average value of pixels from a set of optically black lines in the image sensor. the pixels are averaged as if they were light- sensitive and passed through the appropriate gain. this line average is then digitally low-pass filtered over many frames to remo ve temporal noise and random instabilities associated with this measurement. the new filtered average is then compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. if the average is lower than the minimum acceptable level, the offset correc- tion value is increased by a predetermined am ount. if it is above the maximum level, the offset correction value is decreased by a predetermined amount. the high and low thresholds have been calculated to avoid os cillation of the black level from below to above the targeted black level. row-wise noise correction row (line)-wise noise correction is handled automatically by the image sensor. no adjustments are provided except to enable or disable this feature. clearing r0x3044[10] disables the row noise correction. default se tting is for row noise correction to be enabled. row-wise noise correction is performed by ca lculating an average fr om a set of optically black pixels at the start of each line and th en applying each average to all the active pixels of the line. column correction the MT9M024 uses column parallel readout architecture to achieve fast frame rate. without any corrections, the consequence of this architecture is that different column signal paths have slightly different offsets that might show up on the final image as structured fixed pattern noise. MT9M024 has column correction circuitry that measures this offset and removes it from the image before output. this is done by samp ling dark rows contai ning tied pixels and measuring an offset coefficient per column to be corrected later in the signal path.
MT9M024_ds rev. g pub. 4/15 en 38 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features column correction can be enabled/disabled via r0x30d4[15]. additionally, the number of rows used for this offset coefficient me asurement is set in r0x30d4[3:0]. by default this register is set to 0x7, which means that 8 rows are used. this is the recommended value. other control features regarding column correction can be viewed in the MT9M024 register reference. any changes to column correction settings need to be done when the sensor streaming is disabl ed and the appropriate triggering sequence must be followed as described below. column correction triggering column correction requires a special procedure to trigger depending on which state the sensor is in. column triggering on startup when streaming the sensor for the first time after powerup, a special sequence needs to be followed to make sure that the column correction coefficients are internally calcu- lated properly. 1. follow proper power up sequen ce for power supplies and clocks. 2. apply sequencer settings if needed (linear or hdr mode). 3. apply frame timing and pll settin gs as required by application. 4. set analog gain to 1x and low conversion gain (r0x30b0=0x1300) 5. enable column correction and settings (r0x30d4=0xe007). 6. disable auto re-trigger for change in conver sion gain or col_gain, and enable column correction always (r0x30ba = 0x0008). 7. enable streaming (r0x301a[2]=1)or drive the trigger pin high. 8. wait 9 frames to settle (first frame after co ming up from standby is internally column correction disabled). 9. disable streaming (r0x301a[2]=0). after this, the sensor has calculated the proper column correction coefficients and the sensor is ready for streaming. any other settings (including gain, integration time and conversion gain etc.) can be done afterwards without affecting column correction. column correction retriggering due to mode change since column offsets is sensitive to changes in the analog signal path, such changes require column correction circuitry to be retriggered for the new path. examples of such mode changes include: horizontal mirror, vert ical mirror, changes to column correction settings. when such changes take place, the fo llowing sequence needs to take place: 1. disable streaming (r0x301a[2]=0) or drive the trigger pin low. 2. enable streaming (r0x301a[2]=1) or drive the trigger pin high. 3. wait 9 frames to settle. note: the above steps are not needed if the sensor is being reset (soft or hard reset) upon the mode change. defective pixel correction defective pixel correction is intended to compensate for defective pixels by replacing their value with a value based on the surrounding pixels, making the defect less notice- able to the human eye. the defect pixel correction feature supports up to 200 defects.
MT9M024_ds rev. g pub. 4/15 en 39 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor features the locations of defective pixels are stored in a table on chip du ring the manufacturing process; this table is accessible through the two-wire serial interface. there is no provi- sion for later augmenting the defect table entries. the dpc algorithm is one-dimensional, calc ulating the resulting averaged pixel value based on nearby pixels within a row. the algorithm distinguishes between color and monochrome parts; for color parts, the algo rithm uses nearest neighbor in the same color plane. at high gain, long exposure, and high temp erature conditions, the performance of this function can degrade. test patterns the MT9M024 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. with one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. test patterns are selected by test_pattern_mode register (r0x3070). only one of the test patterns can be enabled at a given point in time by sett ing the test_pattern_mode register according to table 9. when test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in test_pat- tern_green (r0x3074 and r0x3078) for green pixels, test_pattern_blue (r0x3076) for blue pixels, and test_pattern_red (r0x3072) for red pixels. note: turn off black level calibration (blc) when test pattern is enabled. color field when the color field mode is selected, the value for each pixel is determined by its color. green pixels will receive the value in test_pattern_green, red pixels will receive the value in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. vertical color bars when the vertical color bars mode is select ed, a typical color bar pattern will be sent through the digital pipeline. walking 1s when the walking 1s mode is selected, a wa lking 1s pattern will be sent through the digital pipeline. the first value in each row is 1. table 9: test pattern modes test_pattern_mode test pattern output 0 no test pattern (normal operation) 1 solid color test pattern 2 100% color bar test pattern 3 fade-to-gray color bar test pattern 256 walking 1s test pattern (12-bit)
MT9M024_ds rev. g pub. 4/15 en 40 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the MT9M024.the interface protoc ol uses a master/slave model in which a master controls one or more slave devices. th e sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize trans- fers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire seri al interface specific ation allow the slave device to drive s clk low; the MT9M024 uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high.
MT9M024_ds rev. g pub. 4/15 en 41 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor two-wire serial register interface slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the MT9M024 are 0x20 (write address) and 0x21 (read address) in accordance with the specificatio n. alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr input. an alternate slave address can al so be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transf er. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence . the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s inte rnal register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
MT9M024_ds rev. g pub. 4/15 en 42 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 24) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. figure 24 shows how the internal register address maintained by the MT9M024 is loaded and incremented as the sequence proceeds. figure 24: single read from random location single read from current location this sequence (figure 25) performs a read using the current value of the MT9M024 internal register address. the master terminates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 25: single read from current location sequential read, start from random location this sequence (figure 26) starts in the same way as the single read from random loca- tion (figure 24). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 26: sequential read, start from random location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+ 1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p a a a a
MT9M024_ds rev. g pub. 4/15 en 43 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor two-wire serial register interface sequential read, start from current location this sequence (figure 27) starts in the same way as the single read from current loca- tion (figure 25). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 27: sequential read, start from current location single write to random location this sequence (figure 28) begins with the ma ster generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 28: single write to random location sequential write, start at random location this sequence (figure 29) starts in the same way as the single write to random location (figure 28). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the writ e is terminated by the master generating a st op condition. figure 29: sequential write, start at random location read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+ 1 a a write data slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
MT9M024_ds rev. g pub. 4/15 en 44 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor spectral characteristics spectral characteristics figure 30: quantum efficiency C color sensor 0 10 20 30 40 50 60 70 red green blue 350 wavelength (nm) quantum efficiency (%) 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050
MT9M024_ds rev. g pub. 4/15 en 45 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor spectral characteristics figure 31: estimated quantum efficiency C monochrome sensor
MT9M024_ds rev. g pub. 4/15 en 46 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications electrical specifications unless otherwise stated, the following specif ications apply to the following conditions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; t a = -30 c to +70 c; output load = 10pf; frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 32 and table 10. figure 32: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 10: two-wire seri al bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard-mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time: t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
MT9M024_ds rev. g pub. 4/15 en 47 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications notes: 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automa tically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. i/o timing by default, the MT9M024 launches pixel data, fv, and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv, and lv using the rising edge of pixclk. this can be changed using register r0x3028. see figure 33 and table 11 for i/o timing (ac) characteristics. rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance cin_si - 3.3 - 3.3 pf s data max load capacitance cload_sd - 30 - 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ? table 10: two-wire seri al bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard-mode fast-mode unit min max min max
MT9M024_ds rev. g pub. 4/15 en 48 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications figure 33: i/o timing diagram notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c at 2.5 v, and -30 c at 3.1 v. all values are taken at the 5 0% transition point. the loading used is 10 pf. 2. jitter from pixclk is already taken into account as the data of all the output parameters. table 11: i/o timing characteristics (2.8v v dd _io) 1 symbol definition condition min typ max unit f extclk input clock frequency 6 C 50 mhz t extclk input clock period 20 C 166 ns t r input clock rise time C 3 C ns t f input clock fall time C 3 C ns t jitter input clock jitter C C 600 ps t rp pixclk rise time pclk slew rate = 6 1.2 C 2.9 ns t fp pixclk fall time pclk slew rate = 6 1.2 C 2.9 ns pixclk duty cycle 45 50 55 % f pixclk pixclk frequency 2 6 C 74.25 mhz t pd pixclk to data valid pclk slew rate = 6, parallel slew rate = 7 C2 C 2.5 ns t pfh pixclk to fv high pclk slew rate = 6, parallel slew rate = 7 C2 C 2.5 ns t plh pixclk to lv high pclk slew rate = 6, parallel slew rate = 7 C2 C 2.5 ns t pfl pixclk to fv low pclk slew rate = 6, parallel slew rate = 7 C2 C 2.5 ns t pll pixclk to lv low pclk slew rate = 6, parallel slew rate = 7 C2 C 2.5 ns data[11:0] line_valid/ pixclk extclk t r t extclk t f frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. t plh t pfh t pfl t pll t pd pxl _0 pxl _1 pxl _2 pxl _n 90% 10% t rp t fp 90% 10% frame_valid
MT9M024_ds rev. g pub. 4/15 en 49 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c at 1.7 v, and -30 c at 1.95v. all values are taken at the 50 % transition point. the loading used is 10 pf. 2. jitter from pixclk is already taken into account as the data of all the output parameters. notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c at 2.5v, and -30 c at 3.1 v. the loading used is 10 pf. table 12: i/o timing characteristics (1.8v v dd _io) 1 symbol definition condition min typ max unit f extclk input clock frequency 6-50mhz t extclk input clock period 20 - 166 ns t r input clock rise time -3-ns t f input clock fall time -3-ns t jitter input clock jitter C C 600 ps t rp pixel rise time pclk slew rate = 6 1.8 - 4.8 ns t fp pixel fall time pclk slew rate = 6 1.7 - 4.5 ns pixel duty cycle 45 50 55 % f pixclk pixclk frequency 2 674.25mhz t pd pixclk to data valid pclk slew rate = 6, parallel slew rate = 7 C2.5 C 2 ns t pfh pixclk to fv high pclk slew rate = 6, parallel slew rate = 7 C2.5 C 2 ns t plh pixclk to lv high pclk slew rate = 6, parallel slew rate = 7 C2.5 C 2 ns t pfl pixclk to fv low pclk slew rate = 6, parallel slew rate = 7 C2.5 C 2 ns t pll pixclk to lv low pclk slew rate = 6, parallel slew rate = 7 C2.5 C 2 ns table 13: i/o rise slew rate (2.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 1.08 1.77 2.72 v/ns 6 default 0.77 1.26 1.94 v/ns 5 default 0.58 0.95 1.46 v/ns 4 default 0.44 0.70 1.08 v/ns 3 default 0.32 0.51 0.78 v/ns 2 default 0.23 0.37 0.56 v/ns 1 default 0.16 0.25 0.38 v/ns 0 default 0.10 0.15 0.22 v/ns
MT9M024: 1/3-inch cmos digital image sensor electrical specifications MT9M024_ds rev. g pub. 4/15 en 50 ?semiconductor components industries, llc,2015. notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c at 2.5 v, and -30 c at 3.1v. the loading used is 10 pf. notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c at 1.7 v, and -30 c at 1.95v. the loading used is 10 pf. notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c at 1.7 v, and -30 c at 1.95v. the loading used is 10 pf. table 14: i/o fall slew rate (2.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 1.00 1.62 2.41 v/ns 6 default 0.76 1.24 1.88 v/ns 5 default 0.60 0.98 1.50 v/ns 4 default 0.46 0.75 1.16 v/ns 3 default 0.35 0.56 0.86 v/ns 2 default 0.25 0.40 0.61 v/ns 1 default 0.17 0.27 0.41 v/ns 0 default 0.11 0.16 0.24 v/ns table 15: i/o rise slew rate (1.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.41 0.65 1.10 v/ns 6 default 0.30 0.47 0.79 v/ns 5 default 0.24 0.37 0.61 v/ns 4 default 0.19 0.28 0.46 v/ns 3 default 0.14 0.21 0.34 v/ns 2 default 0.10 0.15 0.24 v/ns 1 default 0.07 0.10 0.16 v/ns 0 default 0.04 0.06 0.10 v/ns table 16: i/o fall slew rate (1.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.42 0.68 1.11 v/ns 6 default 0.32 0.51 0.84 v/ns 5 default 0.26 0.41 0.67 v/ns 4 default 0.20 0.32 0.52 v/ns 3 default 0.16 0.24 0.39 v/ns 2 default 0.12 0.18 0.28 v/ns 1 default 0.08 0.12 0.19 v/ns 0 default 0.05 0.07 0.11 v/ns
MT9M024_ds rev. g pub. 4/15 en 51 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications dc electrical characteristics the dc electrical characteristics are shown in the tables below. table 17: dc electrical characteristics caution stresses greater than those listed in table 14 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. notes: 1. exposure to absolute maximum rating cond itions for extended periods may affect reliability. 2. to keep dark current and shot noise artifacts fr om impacting image quality, keep operating tem- perature at a minimum. symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 1.7/2.5 1.8/ 2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage for slvs mode 0.3 0.4 0.6 v v dd _slvs hispi supply voltage for hivcm mode 1.7 1.8 1.95 v v ih input high voltage v dd _io*0.7 C C v v il input low voltage C C v dd _io*0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd CC20 ? a v oh output high voltage v dd _io-0.3 C C v v ol output low voltage C C 0.4 v i oh output high current at specified v oh -22 C C ma i ol output low current at specified v ol CC22ma table 18: absolute maximum ratings symbol parameter minimum maximum unit symbol v supply power supply voltage (all supplies) C0.3 4.5 v v supply i supply total power supply current C 200 ma i supply i gnd total ground current C 200 ma i gnd v in dc input voltage C0.3 v dd _io + 0.3 v v in v out dc output voltage C0.3 v dd _io + 0.3 v v out t stg 1 storage temperature C40 +150 c t stg 1
MT9M024_ds rev. g pub. 4/15 en 52 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications notes: 1. operating currents are measur ed at the following conditions: v aa = v aa _pix = v dd _io = v dd _pll = 2.8 v v dd =1.8 v pll enabled and pixclk = 74.25 mhz t a = 25 c c load = 10 pf measured in dark table 20: operating current consumption in parallel output and hdr mode notes: 1. operating currents are measur ed at the following conditions: v aa = v aa _pix = v dd _io = v dd _pll = 2.8 v v dd = 1.8 v pll enabled and pixclk = 74.25 mhz t a = 25 c c load = 10 pf measured in dark table 19: operating current consumption in parallel output and linear mode definition condition symbol min typ max unit digital operating current stre aming, 1280x960 45 fps i dd 1 C 63 90 ma i/o digital operating current st reaming, 1280x960 45 fps i dd _io C 35 40 ma analog operating current stre aming, 1280x960 45 fps i aa C 30 45 ma pixel supply current streaming, 1280x960 45 fps i aa _pix C 10 15 ma pll supply current streaming, 1280x960 45 fps i dd _pll C 7 15 ma digital operating current streaming, 720p 60 fps i dd 1 C 63 90 ma i/o digital operating current streaming, 720p 60 fps i dd _io - 35 40 ma analog operating current streaming, 720p 60 fps i aa C 30 45 ma pixel supply current streaming, 720p 60 fps i aa _pix C 10 15 ma pll supply current streaming, 720p 60f ps i dd _pll C 7 15 ma definition condition symbol min typ max unit digital operating current stre aming, 1280x960 45 fps i dd C95115 ma i/o digital operating current st reaming, 1280x960 45 fps i dd _io C 35 40 ma analog operating current stre aming, 1280x960 45 fps i aa C 65 75 ma pixel supply current streaming, 1280x960 45 fps i aa _pix C 15 20 ma pll supply current streaming, 1280x960 45 fps i dd _pll C 7 15 ma digital operating current streaming, 720p 60 fps i dd C95115ma i/o digital operating current streaming, 720p 60 fps i dd _io C 35 40 ma analog operating current streaming, 720p 60 fps i aa C 61 75 ma pixel supply current streaming, 720p 60 fps i aa _pix C 15 20 ma pll supply current streaming, 720p 60 fps i dd _pll C 7 15 ma
MT9M024_ds rev. g pub. 4/15 en 53 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications notes: 1. operating currents are measur ed at the following conditions: v aa = v aa _pix = v dd _io = v dd _pll = 2.8v v dd = 1.8v v dd _slvs = 0.4v (lovcm) v dd _slvs = 1.8v (hivcm) pll enabled and pixclk = 74.25 mhz t a = 25 c cload = 10pf measured in dark table 21: operating currents in hispi output and linear mode definition condition symbol min typ max unit digital operating current streaming 1280x960 45 fps i dd C95115ma i/o digital operating current s treaming 1280x960 45 fps i dd _io C 100 150 ? a analog operating current str eaming 1280x960 45 fps i aa C3045ma pixel supply current streaming 1280x960 45 fps i aa _pix C 10 15 ma pll supply current streaming 1280x960 45 fps i dd _pll C 7 15 ma slvs supply current current lovcm mode streaming 1280x960 45 fps i dd _slvs C 8 15 ma current hivcm mode streaming 1280x960 45 fps C1625ma digital operating current streaming 720p 60 fps i dd C95115ma i/o digital operating current streaming 720p 60 fps i dd _io C 100 150 ? a analog operating current streaming 720p 60 fps i aa C3045ma pixel supply current streaming 720p 60 fps i aa _pix C 10 15 ma pll supply current streaming 720p 60 fps i dd _pll C 7 15 ma slvs supply current current lovcm mode streaming 720p 60 fps i dd _slvs C 8 15 ma current hivcm mode streaming 1280x960 60 fps C1625ma
MT9M024_ds rev. g pub. 4/15 en 54 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications notes: 1. operating currents are measur ed at the following conditions: v aa = v aa _pix = v dd _io = v dd _pll = 2.8 v v dd = 1.8 v v dd _slvs = 0.4 v (lovcm) v dd _slvs = 1.8 v (hivcm) pll enabled and pixclk=74.25 mhz t a = 25 c cload = 10 pf measured in dark table 22: operating current in hispi output and hdr mode definition condition symbol min typ max unit digital operating current streaming 1280x960 45 fps i dd C 115 130 ma i/o digital operating current streaming 1280x960 45 fps i dd _io C 100 150 ? a analog operating current str eaming 1280x960 45 fps i aa C6575ma pixel supply current streaming 1280x960 45 fps i aa _pix C 15 20 ma pll supply current streaming 1280x960 45 fps i dd _pll C 7 15 ma slvs supply current current lovcm mode streaming 1280x960 45 fps i dd _slvs C 8 15 ma current hivcm mode streaming 1280x960 45 fps C1625ma digital operating current streaming 720p 60 fps i dd C 115 130 ma i/o digital operating current streaming 720p 60 fps i dd _io C 100 150 ? a analog operating current streaming 720p 60 fps i aa C6575ma pixel supply current streaming 720p 60 fps i aa _pix C 15 20 ma pll supply current streaming 720p 60 fps i dd _pll C 7 15 ma slvs supply current current lovcm mode streaming 720p 60 fps i dd _slvs C 8 15 ma current hivcm mode streaming 1280x960 60fps C1625ma
MT9M024_ds rev. g pub. 4/15 en 55 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications notes: 1. analog C v aa + v aa _ pix + v dd _ pll 2. digital C v dd + v dd _io figure 34: power supply rejection ratio table 23: standby current consumption definition condition symbol min typ max unit hard standby (clock off) analog, 2.8 v CC 30 100 a digital, 1.8 v C C 85 2500 a hard standby (clock on) analog, 2.8 v C C 30 100 a digital, 1.8 v CC1.55 4 ma soft standby (clock off) analog, 2.8 v CC 85 100 a digital, 1.8 v C C 85 2500 a soft standby (clock on) analog, 2.8 v CC 30 100 a digital, 1.8 v CC1.55 4 ma 0 10 20 30 40 50 60 70 1000 10000 100000 1000000 p s r r ? ( d b ) frequency ? (hz) power ? supply ? rejection ? ratio
MT9M024_ds rev. g pub. 4/15 en 56 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications hispi electrical specifications the hispi transmitter electrical specifications are listed at 700 mhz. table 24: input voltage and current (hispi power supply 0.4 v) measurement conditions: max freq 700 mhz parameter symbol min typ max unit supply current ( pwr hispi) (driving 100 ? load) i dd _slvs C 10 15 a hispi common mode voltage (driving 100 ? load) v cmd v dd _slvs x 0.45 v dd _slvs/2 v dd _slvs x 0.55 v hispi differential output voltage (driving 100 ? load) |v od |v dd _slvs x 0.36 v dd _slvs/2 v dd _slvs x 1.64 v change in v cm between logic 1 and 0 ? v cm 25 mv change in |v od | between logic 1 and 0 |v od |25mv vod noise margin nm -30 30 difference in v cm between any two channels | ? v cm |50mv difference in v od between any two channels | ? v od |100mv common-mode ac voltage (pk) without v cm cap termination ? v cm _ac 50 mv common-mode ac voltage (pk) with v cm cap termination ? v cm _ac 25 mv max overshoot peak |v od |v od _ac 1.2*|v od |v max overshoot vdiff pk-pk v diff_pkpk 2.4*|v od |v eye height v eye 0.5*v dd _slvs single-ended output impedance ro 35 50 70 ? output impedance mismatch ? ro 20 % table 25: input voltage and current (hispi power supply 1.8 v) measurement conditions: max freq 700 mhz parameter symbol min typ max unit supply current ( pwr hispi) (driving 100 ? load) i dd _hivcm C 15 25 ma hispi common mode voltage (driving 100 ? load) v cmd 0.76 0.9 1.07 v hispi differential output voltage (driving 100 ? load) |v od | 200 280 350 v change in v cm between logic 1 and 0 ? v cm 25 change in |v od | between logic 1 and 0 ?? v od |25 v od noise margin nm -30 30 difference in v cm between any two channels ?? v cm |50 difference in v od between any two channels ?? v od |100 common-mode ac voltage (pk) without v cm cap termination ? v cm _ac 50 common-mode ac voltage (pk) with v cm cap termination ? v cm _ac 30
MT9M024_ds rev. g pub. 4/15 en 57 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications figure 35: differential output voltage for clock or data pairs notes: 1. one ui is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. taken from 0v crossing point w/ dll off. 3. also defined with a maximum loading capacitance of 10pf on any pin. the loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point. max overshoot peak |v od |v od _ac 1.2*|v od | max overshoot vdiff pk-pk v diff_pkpk 2.4*|v od |v eye height v eye 320 single-ended output impedance ro 40 70 100 output impedance mismatch ? ro 20 % table 26: rise and fall times measurement conditions: hispi power su pply 0.4v or 1.8v, max freq 700 mhz parameter symbol min typ max unit data rate 1/ui 280 C 700 mb/s max setup time from transmitter txpre 0.3 C C ui 1 max hold time from transmitter txpost 0.3 C C ui clock jitter (rms) clk jitter C 50 C ps rise time (20% - 80%) rise C 0.325ui C fall time (20% - 80%) fall 150ps 0.3 ui C clock duty pll_duty 45 50 55 % bitrate period t pw 1.43 3.57 ns 1 eye width t eye 0.3 ui 1, 2 data total jitter (pk pk)@1e-9 tt otaljit 0.2 ui 1, 2 clock period jitter(rms) t ckjit 50 ps 2 clock cycle to cycle jitter (rms) t cyjit 100 ps 2 clock to data skew t chskew -0.1 0.1 ui 1, 2 phy-to-phy skew t physkew 2.1 ui 1, 5 table 25: input voltage and current (hispi power supply 1.8 v) measurement conditions: max freq 700 mhz parameter symbol min typ max unit 0v diff) vdiffmax vdiffmin output signal is 'cp - cn' or 'dp - d
MT9M024_ds rev. g pub. 4/15 en 58 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor electrical specifications figure 36: eye diagram for clock and data signals figure 37: skew within the phy and output channels clkjitter t rigger/ reference vdiff max vdiff ui/ 2 ui/ 2 vdiff txpre txpost clock mask data mask rise fall 20% 80% tcmpskew vcmd tc hskew1phy
MT9M024_ds rev. g pub. 4/15 en 59 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor power-on reset and standby timing power-on reset and standby timing power-up sequence the recommended power-up sequence for the MT9M024 is shown in figure 29. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. turn on v dd _pll power supply. 2. after 0?10 ? s, turn on v aa and v aa _pix power supply. 3. after 0?10 ? s, turn on v dd _io power supply. 4. after the last power supply is stable, enable extclk. 5. assert reset_bar for at least 1ms. 6. wait 850000 extclks (for internal initialization into software standby). 7. configure pll, output, and image settings to desired values. 8. wait 1ms for the pll to lock. 9. set streaming mode (r0x301a[2] = 1). figure 38: power up v dd _pll (2.8) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) extclk reset_b t0 t1 t2 t3 tx t4 t5 t6 hard reset internal initialization software standby pll lock streaming
MT9M024_ds rev. g pub. 4/15 en 60 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor power-on reset and standby timing notes: 1. xtal settling time is component-de pendent, usually taking about 10 C 100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc ti me must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. table 27: power-up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix 3 t0 0 10 C ? s v aa /v aa _pix to v dd _io t1 0 10 C ? s v dd _io to v dd t2 0 10 C ? s v dd to v dd _slvs t3 0 10 C ? s xtal settle time tx C 30 1 Cms hard reset t4 1 2 CC ms internal initialization t5 850000 C C extclks pll lock time t6 1 C C ms
MT9M024_ds rev. g pub. 4/15 en 61 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor power-on reset and standby timing power-down sequence the recommended power-down sequence for the MT9M024 is shown in figure 30. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. power may be removed from all supplies simultaneously, and a sudden loss of power on all rails does no t cause damage or affect the lifetime of the device. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 39: power down note: t4 is required between power down and next po wer up time; all decoupling caps from regulators must be completely discharged. table 28: power-down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd t0 0 C C ? s v dd to v dd _io t1 0 C C ? s v dd _io to v aa /v aa _pix t2 0 C C ? s v aa /v aa _pix to v dd _pll t3 0 C C ? s pwrdn until next pwrup time t4 100 C C ms v dd _io (1.8/2.8) t4 t 0 t1 t3 t2 extclk v dd _slvs (0.4) v dd (1.8) v aa _pix v aa (2.8) v dd _pll (2.8) power down until next power up cycle
MT9M024_ds rev. g pub. 4/15 en 62 ?semiconductor components industries, llc,2015 MT9M024: 1/3-inch cmos digital image sensor package dimensions package dimensions figure 40: 63-ball ibga package outline drawing
MT9M024_ds rev. g pub. 4/15 en 63 ?semiconductor components industries, llc,2015 MT9M024: 1/3-inch cmos digital image sensor package dimensions note: all dimensions are in millimeters.
MT9M024_ds rev. g pub. 4/15 en 64 ?semiconductor components industries, llc,2015. MT9M024: 1/3-inch cmos digital image sensor revision history revision history rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15 ? updated ?ordering information? on page 2 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/15 ? converted to on semiconductor template ? removed confidential marking rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/22/13 ? updated temperature range in ?general description? on page 1 ? updated figure 2: ?typical configuratio n: serial four-lane hispi interface,? on page 2 ? updated figure 3: ?typical configuration: parallel pixel data interface,? on page 3 ? updated ?pixel array structure? on page 7 ? updated figure 6: ?pixel color pattern detail (top right corner),? on page 8 ? updated ?default readout order? on page 8 ? added ?digital gain control? on page 9 ? added ?dll timing adjustment? on page 13 ? updated ?exposure? on page 16 ? updated equation 2 on page 16 ? updated table 8, ?real-time context-switch registers,? on page 21 ? updated ?pll-generated master clock? on page 22 ? updated ?hard standby? on page 24 ? updated title of figure 19: ?eight pixels in normal and column mirror readout modes,? on page 25 ? added note at the end of ?embedded data and statistics? on page 29 ? updated ?embedded data? on page 30 ? updated figure 23: ?format of embedded statistics output within a frame,? on page 31 ? updated ?column triggering on startup? on page 33 ? updated ?column correction retriggering due to mode change? on page 33 ? updated ?i/o timing? on page 42 ? updated figure 33: ?i/o timing diagram,? on page 43 ? deleted table 9, ?i/o timing characteristics ? added table 11, ?i/o timing charac teristics (2.8v vdd_io)1,? on page 43 ? added table 12, ?i/o timing characteristics (1.8v vdd_io)1,? on page 44 ? added table 13, ?i/o rise slew rate (2.8v vdd_io)1,? on page 44 ? added table 14, ?i/o fall slew rate (2.8v vdd_io)1,? on page 45 ? added table 15, ?i/o rise slew rate (1.8v vdd_io)1,? on page 45 ? updated table 20, ?operating current co nsumption in parall el output and hdr mode,? on page 47 ? added figure 34: ?power supply rejection ratio,? on page 50 ? updated ?power-up sequence? on page 54 ? updated table 27, ?power-up sequence,? on page 55 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/10/12 ? updated table 1, ?pin descriptions, 9 x 9 mm, 63-ball ibga,? on page 5 ? updated figure 4: ?9 x 9 mm 63-ball ibga package,? on page 4
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. MT9M024: 1/3-inch cmos digital image sensor revision history MT9M024_ds rev. g pub. 4/15 en 65 ?semiconductor components industries, llc,2015 . ? updated ?hard standby? on page 24 ? updated ?embedded data and statistics? on page 29 ? updated table 11, ?i/o timing characteristics (2.8v vdd_io)1,? on page 43 ? updated table 24, ?input voltage and current (hispi power supply 0.4 v),? on page 51 ? updated table 25, ?input voltage and current (hispi power supply 1.8 v),? on page 51 ? updated table 26, ?rise and fall times,? on page 52 ? deleted old table 20, ?channel, phy, and intra-phy skew rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/29/11 ? updated table 1, ?key parameters,? on page 1 ? updated table 2, ?available part numbers,? on page 1 ? updated ?exposure? on page 16 ? updated ?hdr specific exposure settings? on page 19 ? updated ?motion compensation? on page 20 ? updated ?pll-generated master clock? on page 22 ? table 8, ?real-time context-switch regist ers,? on page 21updated ?hard standby? on page 24 ? updated figure 19: ?eight pixels in normal and column mirror readout modes,? on page 25 ? updated table 17, ?dc electric al characteristics,? on page 46 ? updated notes for table 19, ?operating curr ent consumption in parallel output and linear mode ,? on page 47 and table 20, ?operating current consumption in parallel output and hdr mode,? on page 47 ? updated table 22, ?operating current in hispi output and hdr mode,? on page 49 ? updated table 23, ?standby current consumption ,? on page 50 ? updated conditions for table 26, ?rise and fall times,? on page 52 and table 22, ?channel, phy, and intra-phy skew,? on page 45 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/19/10 ? updated table 1, ?key parameters,? on page 1 ? updated table 10, ?two-wire serial bus characteristics,? on page 41 ? updated storage temperature max in ta ble 18, ?absolute maximum ratings,? on page 46 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/20/10 ?initial release

▲Up To Search▲

Price & Availability of MT9M024

	To Download MT9M024 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .